#define CPUID_VENDOR_AMD 'AuthenticAMD' #define CPUID_VENDOR_AMD_OLD 'AMDisbetter!' // Early engineering samples of AMD K5 processor #define CPUID_VENDOR_INTEL 'GenuineIntel' #define CPUID_VENDOR_VIA 'VIA VIA VIA ' #define CPUID_VENDOR_TRANSMETA 'GenuineTMx86' #define CPUID_VENDOR_TRANSMETA_OLD 'TransmetaCPU' #define CPUID_VENDOR_CYRIX 'CyrixInstead' #define CPUID_VENDOR_CENTAUR 'CentaurHauls' #define CPUID_VENDOR_NEXGEN 'NexGenDriven' #define CPUID_VENDOR_UMC 'UMC UMC UMC ' #define CPUID_VENDOR_SIS 'SiS SiS SiS ' #define CPUID_VENDOR_NSC 'Geode by NSC' #define CPUID_VENDOR_RISE 'RiseRiseRise' #define CPUID_VENDOR_VORTEX 'Vortex86 SoC' #define CPUID_VENDOR_AO486 'MiSTer AO486' #define CPUID_VENDOR_AO486_OLD 'GenuineAO486' #define CPUID_VENDOR_ZHAOXIN ' Shanghai ' #define CPUID_VENDOR_HYGON 'HygonGenuine' #define CPUID_VENDOR_ELBRUS 'E2K MACHINE ' // Vendor strings from hypervisors. For example, if we want the Vendor ID String (see below), we should code something like that: The idea of the CPUID instruction is that you can call it with different values in EAX, and it will return different information about the processor. This avoids problems with CPUs that do support CPUID but don't support the ID bit in EFLAGS and is likely to be faster for CPUs that do support CPUID (and slower for CPUs that don't). Note 2: You can simply attempt to execute the CPUID instruction and see if you get an invalid opcode exception. The are also CPUs that support CPUID if and only if it has to be enabled first (Cyrix M1). Note 1: There are some old CPUs where CPUID is supported but the ID bit in EFLAGS is not (NexGen). Pushfd Save EFLAGS pushfd Store EFLAGS xor dword, 0x00200000 Invert the ID bit in stored EFLAGS popfd Load stored EFLAGS (with ID bit inverted) pushfd Store EFLAGS again (ID bit may or may not be inverted) pop eax eax = modified EFLAGS (ID bit may or may not be inverted) xor eax, eax = whichever bits were changed popfd Restore original EFLAGS and eax, 0x00200000 eax = zero if ID bit can't be changed, else non-zero ret

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